This is a CMOS LSI generating a two-phase clock signal of low output impedance to drive MN3000 series BBD. Built-in Vgg power supply circuit for the MN3000 series BBD* provides the most suitable Vgg voltage for the BBD when the MN3101 is used with the same power source as BBD. Oscillation is abled by external resistors and capacitors, and also oscillation drive is possible by the separate excitation oscillation. The clock signal frequency is 1/2 of the oscillation frequency.
BBD* Bridge Bucket Delay
