The uPD41464 is a 65,536 word by 4 bit dynamic RAM designed to operate from a single +5 volt power supply and fabricated with a double polylayer, N-channel silicone gate process for high density, high performance, and high reliability. A single transistor storage call and advanced dynamic circuitry ensure minimum power dissipation, while an on chip feature internally generates the negative voltage substrate bias automatically and transparently. The tree state I/O is controlled by -CAS independent of -RAS. After a valid read or hidden refresh cycle, data is held by holding -CAS low. Data input and output is returned to high impedance by returning -CAS high. hidden refreshing allows -CAS to be held low to maintain output data while -RAS us used to execute -RAS only refresh cycles. Refreshing may be accomplished by means of a -CAS before -RAS cycle that internally generates the refresh address, by means of -RAS only refresh cycles, or by normal read or write cycles on the 256 address combinations of A0 through A7 during a 4ms refresh period.
